1. Field of the Invention
The present invention relates to the field of on-chip test circuits. Specifically, the invention is designed to perform a set-up and hold (SUAH) test function.
2. Related Art
In the manufacture of silicon and other microelectronic devices, such as integrated circuits (IC), various testing functions are performed including the active testing of wafers and dies in which the ICs are embedded prior to their isolation. One such test, especially important in testing the functionality of synchronous static random access memories (SRAM) and application specific integrated circuits (ASIC), is the setup and hold (SUAH) test. SUAH testing determines whether SRAM, ASIC, or other integrated circuit designs meet crucial synchronous timing parameter specifications. Setup refers to the time in which a data signal has to be at a certain circuit locus prior to a clock transition signal. Hold refers to the duration of time for which a data signal must be held at a circuit locus after the clock signal has gone to a high value.
With reference to synchronous memories for example, the parameter to be measured is the SUAH time to the clock on input and some of the output registers. Although there is a numerical time value associated with this parameter, its test basically seeks a “go/no go,” or pass/fail result at given time values. In testing this parameter, it has been sometimes difficult to decide the character of the result as pass or fail.
SUAH tests are performed using an external logic analyzing test system, which evokes the pass/fail result. The test system sets a numerical value on the input of the clock. By way of illustration, on the exemplary memory, a 1.5 nanosecond (ns) setup specification is set for test. In this illustration, the test system sets 1.5 ns as the clock pulse time value. The functionality of the circuit under test, in this case the synchronous memory, is checked at that timing value. If the circuit under test is functional at 1.5 ns, the SUAH test result at that value is a pass. Conversely, if the circuit is non-functional at that timing value, the test result is a failure at 1.5 ns. If the memory circuit passes the SUAH test at 1.5 ns, and its functionality must be checked at an even smaller time value, e.g., 1.4 ns, the test system repeats the SUAH test at that value. The SUAH test can be repeated any number of times at sequentially smaller and smaller time values to find the time value point at which the circuit under test will no longer function; e.g., 1.3 ns, 1.25 ns, 1.2 ns, etc.
In the conventional art, a problem arises in the performance of SUAH tests on large scale and especially, very large scale ICs (LSI, VLSI) such as SRAM, in detecting whether or not a circuit passes or fails. On such large systems, in order to detect that a circuit has either passed or failed a SUAH test, a significant number of test vectors are necessary, on the order of hundreds of thousands (105) or millions (106), possibly simply in order to detect whether a single register therein passes or fails. This problem can be illustrated, again using the synchronous memory system, for example. An exemplary SRAM with 18 line address registers requires 218 test vectors, simply to perform SUAH testing on the input latches. SUAH testing in accordance with the conventional art necessitates addressing each and every location in the memory, all 218 of them, to test the input latches. Test data must be written to each and every one of the 218 addresses, and then read back from each and every one of the 218 addresses, to perform a valid SUAH test per the conventional art.
Synchronous SRAM's have clocked input address, data, and control registers/latches. Performance of SUAH tests involves writing data, address, and control bits into the device. In pipelined/complex SRAM components, multiple cascaded registers/latches involve multiple clock cycles to write data to their required addresses. These data must then be read back from their addresses to test the SUAH function and determine if it is a pass or a failure. This read back again may involve multiple clock cycles to shift the outputs of the SRAM to the output buffer. The passage of time involved in the multiple clock cycles required to accomplish these serial tasks further increases the time required to complete SUAH tests, and consequently increases costs involved. This places a substantial overhead burden on testing resources, and is quite significant in terms of the cost of testing in time, resources, and expense.
Accordingly, what is needed is a method and/or circuit for performing SUAH tests with a much lower requisite number of test vectors. What is also needed is a method and/or circuit for performing SUAH tests on memory systems and other ICs without having to writing back into memory. Further, what is needed is a method and or circuit for performing SUAH testing at a register stage without the need to grossly involve other IC stages. Yet further, what is needed is a method and/or circuit for performing SUAH which can substantially reduce the overhead burden on testing resources relative to existing methods and circuits, and further, significantly lower the cost of such testing in time, resources, and expense.